FB2M5LVR 650 nm 10-250 MBd 50 m LC POF Transceiver

At 250 Mbps, the specified reference distance is 50 metres using 0.5 NA step-index POF. At 125 Mbps Ethernet, a point-to-point link can reach 80 metres depending on the installation conditions. The optical figures provide a 14 dB starting budget between the minimum transmit power of −10 dBm and the receiver sensitivity of −24 dBm, before allowances for connectors, fibre attenuation, ageing and temperature. The strongest transmit level is −2 dBm, while the maximum receiver input is 0 dBm, leaving 2 dB before overload on a very short idealised link. Final reach should be checked against the actual cable, connector losses, bends, contamination and required design margin.

The FB2M5LVR handles the physical optical signal rather than implementing a particular network protocol or encoding method. A 100 Mbps Fast Ethernet application using 4B/5B encoding produces a 125 MBd optical symbol rate. An FPGA link carrying 200 Mbps with 8B/10B encoding produces a 250 MBd symbol rate because the encoding adds two transmitted bits for every eight payload bits. This distinction is important when comparing the payload requirement with the maximum signal rate seen by the transceiver. The selected PHY or FPGA must generate the required encoding, idle sequence and clock-recovery behaviour.

The electrical data paths are differential and can be connected to LVDS, CML or LVPECL devices through AC-coupled interface circuits. The receiver provides a typical 1.25 V common-mode level, an 800 mV differential swing and an internal 100 Ω differential termination. An LVDS interface normally operates at a 1.25 V common-mode level, while the CML side is typically biased to 1.5 V and the LVPECL side requires a termination network that establishes 2 V. Coupling capacitors of 100 nF are specified for high-speed operation from approximately 100 to 250 Mbps. Lower data rates may require larger capacitors, and the termination fitted inside the connected PHY, FPGA or ASIC must be checked before finalising the circuit.

The transmitter and receiver enter their sleep states independently. The transmitter sleeps when no data or toning signal is present, while the receiver sleeps when no optical input is detected. Typical sleep currents are 20 µA for the transmitter and 7 µA for the receiver, giving a combined typical value of 27 µA; the combined maximum is 55 µA. Transmitter wake-up takes 5 µs typically and up to 80 µs, with at least 50 mV differential input swing required to trigger wake-up, while receiver wake-up takes 10 µs typically and up to 100 µs. Designs requiring immediate response or continuous link supervision should account for these delays and maintain a suitable idle or toning pattern where necessary.

Correct grounding is required to control crosstalk, external interference and ESD exposure. EMI shield pins 1 and 12 should connect directly to the PCB signal-ground plane, and both transmitter ground pins, 4 and 6, must be connected because they are not internally linked. Differential data tracks should use controlled impedance and matched routing, while power-line capacitors should be positioned close to the relevant supply pins. The housing uses electrically conductive fibre-filled plastic, so conductive PCB traces should not pass beneath its defined seating surfaces. The mechanical footprint should be applied with its stated ±0.2 mm general tolerance to avoid electrical or mechanical conflicts.

The transceiver is not suitable for infrared or vapour-phase reflow soldering. The permitted soldering limit is 260 °C for 10 seconds on one occasion, with heat applied at least 2.2 mm from the lead root, and non-halogenated water-soluble flux is recommended. The optical dust plug should remain fitted during soldering, washing and drying, while suitable alcohol-based cleaning agents may be used; acetone, ethyl acetate and phenol-based products are not permitted. The component is rated MSL 2a, allowing 672 hours or four weeks below 30 °C and 60% relative humidity after opening. An unopened moisture-barrier bag has a 24-month shelf life below 40 °C and 90% relative humidity, while longer opened storage requires a dry cabinet below 10% relative humidity.

The transceiver is intended for systems that need a compact LC plastic-optical-fibre link with differential electrical signalling. Suitable applications include industrial networking, robotic connections, medical data systems and transport-system buses, with Fast Ethernet, EtherCAT, Sercos III and proprietary links identified as possible uses. Selection should take account of the 3.0 to 3.6 V supply, 10 to 250 Mbps signal range, optical budget and −40 °C to +85 °C operating range. It should be paired with a compatible PHY, FPGA or ASIC because protocol handling and encoding are not performed by the optical device. The through-hole soldering process, PCB keepout requirements and LC cable construction should also be considered before the board layout is released.