Analyser Module for PCIe 8Gbps
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PCI-SIG®, PCIe® and the PCI Express® are US registered trademarks and/or service marks of PCI-SI. Keysight Technologies’s PCIe Protocol Analyser is a combination of hardware and software features that ensure the fastest time to insight.
For any analyser at PCIe 3.0 speeds, the key is how to recover the signal accurately in different types of platforms and systems. Keysight Technologies’s PCIe 3.0 analyser uses Keysight Technologies’s unique ESP (Equalization Snoop Probe) technology, with the ability to tune the equalization algorithm used according to the type of channel the analyser is monitoring. This ensures that the data captured in the analyser is exactly what is on the wire. Without this capability, at 8GT/s, there is a high likelihood of misrepresentation of the data on the bus, which can lead to wasted hours, if not days in the validation cycle.
Keysight Technologies’s PCIe analyser combines accurate probing technology with flexible hardware architecture. The analyser hardware supports all three generations, PCIe 1.0 through PCIe 3.0, and supports x1 link width through x16. Keysight Technologies’s Protocol Analysers use a modular chassis based architecture. For additional flexibility, a single x16 configuration can be split into 2 separate smaller link width test systems, providing maximum equipment utilization.
Transactional analysis of NVMe and PCIe data includes the tools to make finding and decoding the information that make it easy to locate the protocol errors or validate device operation. Keysight Technologies’s GUI uses the industry standard spreadsheet style for presentation of protocol information. This makes the viewing of data clear and precise through a table based approach. Keysight Technologies’s protocol viewers include the easy flow feature, and color by packet type feature, to further highlight the stimulus and response nature of the protocols, so it is easy to see the request being sent and the data being received. Viewers for the protocol analyser include Lane, Packet, Navigation, LTSSM, and Performance Summary, showing data from the physical layer up through the transaction layer.
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- Supports 2.5 GT/s (Gen1), 5.0 GT/s (Gen2) and 8.0 GT/s (Gen3) speeds
- Link width support x1 through x16 lanes
- Large capture buffer, up to 8GBytes capture per system (for x16 Link)
- NVMe data analysis with data overview and detailed decoding
- Detailed Performance analysis of throughput and response time
- Lane view with packet highlighting to show the actual data on the bus
- Packet viewer with flexible coloring, color by packet type or direction
- Link Training & Status, State Machine (LTSSM) overview of the physical layer logic sub-block
- Navigation viewer gives quick access to all messages within the trace