Famille ispClock5300S de Lattice

Numéro de référence fabricant :

ispPAC-CLK5304S-01T48C

Fabricant Lattice Semiconductors

Lattice Semiconductors

Description :

The ispClock5300S (single-ended) is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5300S family provides 4 to 20 single-ended ultra low skew outputs.

View our wide range of Digital products

View our portfolio of Semiconductors

See all products from our supplier Lattice Semiconductors

RoHS

RoHS

  • Prix et disponibilités

  • Posez une question à nos experts

    Caractéristiques

  • Four Operating Configurations
  • o Zero delay buffer
  • o Zero delay and non-zero delay buffer
  • o Dual non-zero delay buffer
  • o Non-zero delay buffer with output divider
  • 8MHz to 267MHz Input/Output Operation
  • Low Output to Output Skew (<100ps)
  • Low Jitter Peak-to-Peak (< 70 ps)
  • Up to 20 Programmable Fan-out Buffers
  • o Programmable single-ended output standards and individual enable controls
  •  LVTTL, LVCMOS, HSTL, eHSTL, SSTL
  • o Programmable output impedance
  •  40 to 70Ω in 5Ω increments
  • o Programmable slew rate
  • o Up to 10 banks with individual VCCO and GND
  •  1.5V, 1.8V, 2.5V, 3.3V
  • Fully Integrated High-Performance PLL
  • o Programmable lock detect
  • o Three 'Power of 2 inch output dividers (5-bit)
  • o Programmable on-chip loop filter
  • o Compatible with spread spectrum clocks
  • Precision Programmable Phase Adjustment (Skew) Per Output
  • 8 settings; minimum step size 156ps
  • o Locked to VCO frequency
  • Up to +/- 5ns skew range
  • Coarse and fine adjustment modes
  • Up to Three Clock Frequency Domains
  • Flexible Clock Reference and External Feedback Inputs
  • o Programmable single-ended or differential input reference standards
  •  LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL
  • o Clock A/B selection multiplexer
  • o Programmable Feedback Standards
  •  LVTTL, LVCMOS, SSTL, HSTL
  • o Programmable termination
  • All Inputs and Outputs are Hot Socket Compliant
  • Full JTAG Boundary Scan Test In-System Programming Support
  • Exceptional Power Supply Noise Immunity
  • Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
  • 48-pin and 64-pin TQFP Packages
  • Applications
  • o Circuit board common clock distribution
  • o PLL-based frequency generation
  • o High fan-out clock buffer
  • o Zero-delay clock buffer
Caractéristiques Produits similaires
Famille ispClock5300S  

   produits similaires trouvés

Rechercher des produits similaires
Nombre de Sorties 4.0  
Gamme de fonctionnement de Fréquence d'entrée (MHz 8 to 267  
Gamme de Fréquence de Sortie (MHz) 5 to 267  
Fonctionnement VCO (MHz) 160 to 400  
Compatible avec Largeur du Spectre true  
Interfaces Sortance Buffer (Single-ended) LVTTL, LVCMOS, HSTL, eHSTL, SSTL  
Interfaces Sortance Buffer (Différentiel) None  
Retour PLL External  
Max. Cycle-cycle Jitter (ps pk-pk) 70.0  
Température de Fonctionnement (°C) Commercial  
Boîtier 48 pin TQFP