32GB DDR3 - SDRAM RDIMM
Manufacturer's part number :
This Swissbit module is an industry standard 240-pin 8-byte DDR3 registered SDRAM Dual-In-line Memory Module (RDIMM) which is organized as x72 high speed CMOS memory array. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. De-coupling capacitors, stub resistors, calibration resistors and termination resistors are mounted on the PCB board. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving 'power-down' mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM using the standard I²C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module's organization and several timing parameters. The second 128 bytes are available to the end user.
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- 240-pin 72-bit DDR3 registered Dual-In-Line Double Data Rate synchronous DRAM module for server applications
- Module organization: dual rank 512M x 72
- VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
- 1.5V I/O ( SSTL_15 compatible)
- Ultra Low Profile (ULP)
- JEDEC compatible DDR3 PLL/Register component with parity bit support for address and control bus
- Supports ECC error detection and correction
- On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
- Gold-contact pads
- This module is fully pin and functional compatible to the JEDEC PC3-10600 spec. and JEDEC- Standard MO-269. (see www.jedec.org)
- The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]
- DDR3 - SDRAM component Samsung K4B2G0846C
- 256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
- Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type.
- On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity.
- Refresh. Self Refresh and Power Down Modes.
- ZQ Calibration for output driver and ODT.
- System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern.