De-emphasis Signal Converter with Optional Clock Multiplier
Manufacturer's part number :
The de-emphasis technique is used in the transmission of digital electrical signals at gigabit data rates. De-emphasis is a signal pre-distortion to compensate for signal degradations that occur when transmitting electrical signals with gigabit rates over PC board traces, backplanes, or long cables. With the next generation of serial bus standards operating above 5 Gb/s, sophisticated de-emphasis with multi-tap Finite Impulse Response (FIR) filtering will be needed. Many popular high-speed digital interfaces use de-emphasis, such as PCI Express®, SATA, USB3, QPI, HyperTransport, IEEE 802.3 backplanes (10GBASE-KR, 40GBASE-KR4).
The new N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis. The N4916B can emulate transmitter de-emphasis with one pre- and two post-cursors and individually adjustable de-emphasis levels of up to 12.0 dB. With its DC-coupling it tolerates unbalanced pattern streams that often occur in training sequences. The N4916B is designed to be transparent to jitter when stimulated with jitter on data and clock signal, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. De-emphasis can also be used to compensate for distortions caused by cables, fixtures or test boards in the test set for more precise device characterization results.
Technical Data :
Quote and availability
- Accurate characterisation of multi-gigabit serial interfaces using signal de-emphasis:
- Adjustable de-emphasis for one pre- and 2 post-cursors of 0 to 12 dB
- Supports data rates from 660 Mb/s to 14.2 Gb/s
- Tolerates non-balanced patterns
- Transparent to jitter
- Flexible usage as front-end for J-BERT N4903B, ParBERT 81250A or other pattern generators
- Optional Clock Multiplier(opt. 001)
- Small size
- Programmable via J-BERT N4903B or stand-alone